• University of Ottawa

• CEG 2136

CEG 2136
Lab 3: Arithmetic Logic Unit

Teaching Assistants: Moayad Aloqaily, Heli Amarasinghe
Experiment performed: Oct 7th, 21st and 28th, 2014
Table of Contents
Theoretical Part
1. Introduction of the Lab Page 3
2. Discussion of the Problem Page 3
3. Discussion of Algorithmic Solution Page
3
Design Part
1. Presentation of the Design Methodology Applied To Solving the Lab Problems Page
4
2. Discussion of Used Components Page 5
3. Discussion of Actual Solution Page
9
4. Discuss the Tools Used in the Lab Page
10
5. Discussion of Challenging Problems Page
10
Real Implementation
1. Shown Simulation/Synthesis Results Page 11
2. Verification (Live Demonstration) Page 13
3. Discussion Page 17
Prelab Page 18
Theoretical Part
1. Introduction of Problem
Lab 3 serves as an introduction to the Arithmetic Logic Circuits (ALU) and their
implementation.
ALU is a combinational circuit which can execute any of the 16 micro-operations of Table 1. The
operation to be performed is set by the control word S3-S0 as follows: the control signal S3
selects either the Arithmetic Circuit (AC) or the Logic and Shifting Circuit (LSC) to perform the
operation and send the result to the output C; the control signals S2, S1, and S0 define the
operations to be performed by each circuit (AC or LSC). Along with the AC and LSC, students
learn about controlling the status of a ALU through the use of overflow, sign, zero and carry bits.
This lab help introduces the ideas of building complex circuits as well as the building blocks to
start building a fully functional computer.
2. Discussion of Problem
To be the ALU, there was a need to construct several smaller parts before assembling the entire
construction. This is composed of several 4 bit registers, Arithmetic circuit (AC), a logic and
shifting circuit (LSC), a adder and a state indicator; all controlled by an ALU control input and
data inputs. The LSC, uses the bottom half of the table 1, transferring all the micro-operations to
digital circuit. And repeating the same thing with the top half of table 1, for the AC. Once the two
are completed, they will be combined to create the ALU. The next step, is to create a ALU
status register that checks the carry, sign, zero and overflow.
3. Discussion of Algorithmic Solution
Designing an 4-bit ALU, requires several individual pieces. Firstly a 4-bit register, created from
figure 8. Next a 1-bit LSC unit was created, so that it could be modular. The 1 bit consisted of a
multiplexor with 8 inputs, one for each function or micro-operation. Each micro-operation from
the table 1 for LSC was imputed to the multiplexor, 0, 1, AB, A+B, A xor B, AB`, a left shift and a
right shift, both as inputs. The 1-bit was used to make a 4-bit version. The AC, used 2 sets of
multiplexors connected to a full-adder. Each multiplexor, one for each set of inputs, had 0-7
inputs, 1 for each micro-operation, which were: A+B, A+B+1, A, A+1, A+B`, A+B`+1, A` and
A`+1. These 2 circuits would connect to a multiplexor to select between the AC and LSC. The
last circuit needed is a status checker, that checks for any problems with the ALU’s sign, carry,
zero and overflow. Checking for the carry was done with the AC operation (S3=0) and the carry
bit is 1. The sign bit is 1 when the most significant bit of the ALU is 1. If the circuit is zero, the Bit
Z outputs a 1. Checking for overflow is using the 2 most significant bit and xor them.
Design Part
1. Presentation of the Design Methodology Applied

C = S3’Carry4
S = C3
V = (Carry4 xor Carry3)
Z = (C3 + C2 + C1 + C0)’
2. Discussion of Used Components
4-bit register:
The 4 bit register uses 4 D flip-flops, that are each attached to a clock
(clk) and clear (CLRN). Each register also has one input (X3, X2, X1, X0) and one
output (Y3, Y2, Y1, Y0).
LSC: