New York University ECE-GY 6473 Midterm exam with solutions- Fall 2020.- Midterm Exam - ECE 6473 Problem 1. Implement the following logic functions. Size the transistors such that
Problem 1. Implement the following logic functions. Size the transistors such that the
worst-case delay of each logic gate when driving a load of CL is the same as the unit
inverter when driving the same load. Ass
...[Show More]
New York University ECE-GY 6473 Midterm exam with solutions- Fall 2020.- Midterm Exam - ECE 6473 Problem 1. Implement the following logic functions. Size the transistors such that
Problem 1. Implement the following logic functions. Size the transistors such that the
worst-case delay of each logic gate when driving a load of CL is the same as the unit
inverter when driving the same load. Assume that the nFET and pFET of the unit inverter
have an optimal size of Wn and Wp, respectively. (20 points)
(a) ? = (?. ?. ?) + ?. (? + ? + ?)
(b) ? = (? + ?). ? + (? + ?). ?
Problem 2. Consider the two circuits shown in Figure 1. Both have a fanout of 6, that is,
they must drive a load six times the capacitance of each of the inputs. What is the path
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