University of Florida
EEE 5400
Question 1: Silicon FinFET Design Point Device Parameter L Gate = Channel Length 20nm EOT (equivalent oxide thickness) 1nm Power supply 1.0V Fin thickness 8nm Fin Material Silicon Fin Height 50nm 1. What is the channel sheet charge in units of C/cm2 2. What is the approximate maximum current in units of mA/um 3. What is the approximate Vdsat (dr
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Question 1: Silicon FinFET Design Point Device Parameter L Gate = Channel Length 20nm EOT (equivalent oxide thickness) 1nm Power supply 1.0V Fin thickness 8nm Fin Material Silicon Fin Height 50nm 1. What is the channel sheet charge in units of C/cm2 2. What is the approximate maximum current in units of mA/um 3. What is the approximate Vdsat (drain voltage at saturation) Total current for 1 fin in A 3 1. 2. Question 1: Silicon FinFET Design Point 4 3. Vsat at ~20kV/cm (from graph) 20kV/cm * 20nm =40mV 4. 2.76mA/um x (50+50+ 8)nm=298uA Question 1: Silicon FinFET Design Point 5 Question 2: Graphene Transistor Device Parameter L Gate = Channel Length 20nm EOT (equivalent oxide thickness) 1nm Power supply 1.0V Channel material Graphene 1. What is the channel sheet charge in units of C/cm2 2. What is the approximate maximum current in units of mA/um 3. What is the approximate Vdsat (drain voltage at saturation) 4. Is a Graphene transistor superior to TSMC 5nm FinFET ? 6 1. COX—>No change to problem 1 2. Vsat now 4X higher so 4X more current than problem 1 2.76mA/um X 4 = ~11mA/um 3. Vsat at ~5kV/cm (from graph in problem 2) 5kV/cm * 20nm =10mV So saturates at even lower drain to source voltage 4. Not clear. Small bandgap would lead to high IOFF. So some parameters like mobility and vsat are attractive but velocity saturates at lower electric field. It takes many parameters such as IOFF to make a transistor superior to TSMC 5nm Question 2: Graphene Tra

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