Pennsylvania State University CMPEN 431 1 (18 pts) Pipelining A company has designed a new 11-stage instruction pipeline processor: IF -> ID -> RF -> E1 -> E2 -> E3 -> E4 -> M1 -> M2 -> M3 -> WB In this architecture, IF is for instruction fetch, ID is for instruction decoding, RF is for register file read, E1 E2, E3 and E4 are for ALU execution, M1, ...[Show More]
Category: | EXAM SOLUTIONS |
Number of pages: | 12 |
Language: | English |
Last updated: | 1 month ago |
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